`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   18:39:26 04/02/2013
// Design Name:   clock_divider
// Module Name:   C:/Users/Taylor/Documents/CSE 320/Lab2/Lab2/tb_clock_divider.v
// Project Name:  Lab2
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: clock_divider
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module tb_clock_divider;

	// Inputs
	reg Sys_clk_100mhz;
	reg rst;

	// Outputs
	wire clk_50mhz;

	// Instantiate the Unit Under Test (UUT)
	clock_divider uut (
		.Sys_clk_100mhz(Sys_clk_100mhz), 
		.rst(rst),
		.clk_50mhz(clk_50mhz)
	);
	defparam uut.division = 5;

	initial begin
		// Initialize Inputs
		Sys_clk_100mhz = 0;
		rst = 0;

		// Wait 100 ns for global reset to finish
		#10;
        
		// Add stimulus here
		forever #10 Sys_clk_100mhz <= ~Sys_clk_100mhz;
	end
	initial begin
		#11 rst <= 1;
		#10 rst <= 0;
		#10 rst <= 1;
	end
endmodule